The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
A signal path between a transmitter and a receiver (e.g., a receiver path of a serial data interface) includes a communication channel. For example, the serial data interface may be a high speed serial data interface. A signal transmitted via the communication channel may be modified by noise, interference, and/or frequency-dependent attenuation and dispersion. Frequency-dependent attenuation can introduce distortions into the transmitted signal. For example, the distortions may include inter-symbol interference (ISI) and jitter. The distortions may cause errors in the signal as received by the receiver.
The communication channel may be implemented using differential signaling. Differential signaling can reduce the effects of some forms of interference, such as common mode noise. Equalizers such as Continuous Time Linear Equalizers (CTLEs) may be used in communication channels to partially compensate for channel attenuation. A CTLE may be implemented as a differential amplifier with a fixed or programmable frequency dependent degeneration feature. For example, programmable frequency dependent degeneration may be implemented, which allows adjusting one or more resistance and/or capacitance values in the differential amplifier. The resistance and capacitance values may also define a “roll up point,” which refers to a minimum frequency at which the differential amplifier will start to boost the output signal of the differential amplifier.
FIG. 1 shows a receiver path 100 (e.g., of a serial data receiver) including a communication channel 104, an equalizer 108, an error comparator module 112, and a data comparator module 116. The error comparator module 112 includes a sampler 120, a summer 124, a decision feedback estimation (DFE) module 128, and a slicer 132. The equalizer 108 may be, for example, a switched continuous time linear equalizer (CTLE) or a switched CTLE with an integrated sampler.
The equalizer 108 receives an input signal 136 via the communication channel 104 and generates an output signal 140. Each of the input signal 136 and the output signal 140 may include a differential signal pair. The equalizer 108 performs equalization on the input signal 136 to generate the output signal 140. For example, the equalizer 108 may include a differential amplifier.
The input signal 136 received from the communication channel 104 may include attenuation (e.g., frequency dependent attenuation). For example, the frequency dependent attenuation caused by skin effect and dielectric loss, which are two possible sources of attenuation in the communication channel 104, is proportional to a square root of a frequency and the frequency, respectively. The equalizer 108 compensates for any attenuation in the input signal 136 to generate the output signal 140.
The sampler 120 samples the output signal 140 to generate a sampled signal 144. The summer 124 receives the sampled signal 144 and an output 148 of the DFE module 128. For example, the summer 124 may add one or more signals corresponding to the output 148 to the sampled signal 144 or subtract one or more signals from the sampled signal 144. The slicer 132 receives an output 152 of the summer 124 and determines a digital value corresponding to the input signal 136. The slicer 132 generates a digital output 156 that is, for example, a digital high (e.g., “1”) or a digital low (e.g., “0”). The digital output 156 may correspond to a digital error output. In some implementations, the slicer 132 may determine a multi-bit digital value that corresponds to the input signal 136 and generate a corresponding multi-bit digital output 156. In some implementations, the summer 124 and the DFE module 128 may be omitted and the equalizer 108 is instead connected directly to the slicer 132.
Similarly, the data comparator module 116 includes a sampler 160, a summer 164, a DFE module 168, and a slicer 172. The sampler 160 samples the output signal 140 to generate a sampled signal 176. The summer 164 receives the sampled signal 176 and an output 180 of the DFE module 168. The slicer 172 receives an output 184 of the summer 164 and determines a digital value corresponding to the input signal 136. The slicer 172 generates a digital output 188. The digital output 188 may correspond to a digital data output. In some implementations, the slicer 172 may determine a multi-bit digital value that corresponds to the input signal 136 and generate a corresponding multi-bit digital output 188.
A digital adaptation module 192 receives the digital outputs 156 and 188 from the error comparator module 112 and the data comparator module 116, respectively. The digital adaptation module 192 generates corresponding feedback signals 196-1 and 196-2, referred to collectively as feedback signals 196, based on the digital outputs 156 and 188, and generates a digital output signal 200. The feedback signals 196 are provided to the error comparator module 112 and the data comparator module 116.
The feedback signals 196 include digital-to-analog converter (DAC) values and polarities. The feedback signals 196-1 provided to the error comparator module 112 may also include error inputs. The DFE module 128 generates the output 148 based on the feedback signals 196-1. For example, the DFE module 128 may include one or more DACs and the feedback signals 196-1 correspond to optimal values for digital inputs of the DACs. In this manner, the digital adaptation module 192 adapts, or trains, the DFE module 128 until the optimal values are determined. Similarly, the DFE module 168 generates the output 180 based on the feedback signals 196-2.
A clock such as a data clock 204 is provided to each of the error comparator module 112 and the data comparator module 116. For example, the data clock 204 provided to the error comparator module 112 and the data comparator module 116 may be the same clock.
FIG. 2 shows a receiver path 220 including a communication channel 224, an equalizer 228, an error comparator module 232, an odd data comparator module 236, and an even data comparator module 240. Each of the error comparator module 232, the odd data comparator module 236, and the even data comparator module 240 receive an output 244 of the equalizer 228 and provide respective digital outputs 248, 252, and 256 to a digital adaptation module 260 accordingly. The digital adaptation module 260 provides respective feedback signals 264-1, 264-2, and 264-3 (referred to collectively as feedback signals 264) based on the digital outputs 248, 252, and 256 and generates a digital output 268.
The receiver path 220 may correspond to, for example, an ultra-high speed receiver path. In an ultra-high speed receiver path, each of the error comparator module 232, the odd data comparator module 236, and the even data comparator module 240 may be clocked at half of a data rate (e.g., half of a rate at which the data is received by the receiver path 220). Accordingly, each of the error comparator module 232, the odd data comparator module 236, and the even data comparator module 240 receive a half-rate clock. For example, the odd data comparator module 236 receives an odd data clock 272 and the even data comparator module receives an even data clock 276. The odd data clock 272 and the even data clock 276 have a nominal phase difference of 180 degrees. As shown, the error comparator module 232 receives the odd data clock 272, but the error comparator module 232 may be configured to receive either of the odd data clock 272 or the even data clock 276.